This invention relates to integrated circuit nonvolatile memories, and in particular to flash memories. Flash memories are electrically-erasable nonvolatile memories in which groups of cells can be erased in a single operation.
Numerous types of integrated circuit memory are now well known, as are processes for manufacturing them. One particular type of integrated circuit memory is nonvolatile memory. Nonvolatile memory is referred to as such because it does not lose the information stored in the memory when power is removed from the memory. Nonvolatile memory has many applications in products where the supply of electricity is interruptable. For example, one well known product employing flash memory is PCMCIA or PC cards. PC cards are small credit card-sized packages which contain nonvolatile memory within which a computer program or other information is stored. Such devices allow the user to connect and disconnect the memory card from a computer or other electronic apparatus, without losing the program stored within the memory card.
Nonvolatile memory devices include read only memories (ROM), programmable read only memories (PROM), electrically-erasable read only memories (EEPROM), as well as other types. Within the field of electrically-erasable programmable memories, a certain class of devices is known as flash memory, or flash EEPROMs. Such memories are selectively programmable and erasable, typically with groups of cells being erasable in a single operation.
In conventional flash memories, each memory cell is formed from a transistor having a source, drain, control gate and floating gate. The floating gate is formed between the control gate and the substrate. The presence, or absence, of charge trapped on the floating gate can be used to indicate the contents of the memory cell. Charge trapped on the floating gate changes the threshold voltage of the transistor, enabling detection of its binary condition. FIG. 1A and FIG. 1B mustrate typical prior art flash memory cells.
In most flash memories, charge is placed on, or removed from, the floating gate by operating the memory at conditions outside its normal operating conditions for reading its contents. For example, by adjusting the relative potentials between the gate and the source, drain or channel regions, charge, in the form of electrons, can be caused to be injected onto the floating gate, or removed from the floating gate.
An unfortunate disadvantage of existing flash memory cells is that a high potential must be applied to the control gate to program the floating gate. For example, by placing a high positive voltage such as 8.5 volts on the control gate and grounding the source region, electrons will be pulled from the source onto the floating gate where they will be trapped. The negative charge on the floating gate then can be used to indicate the presence of a xe2x80x9conexe2x80x9d or a xe2x80x9czeroxe2x80x9d in the memory cell. An unfortunate consequence of the requirement of using such a high potential for programming (or erase) is that the peripheral circuitry must be designed to also handle that high potential. In other words, all of the transistors and the accessing circuitry through which the 8.5 volts is applied, must itself be capable of handling the 8.5 volt potential. The high potential also generates leakage currents, and causes hot hole degradation. One such typical prior art NOR flash memory cell is described in U.S. Pat. No. 5,077,691 entitled xe2x80x9cFlash EEPROM Array with Negative Gate Voltage Erase Operation.xe2x80x9d
As a result, it would be desirable to provide a flash memory which operates at a lower potential, minimizing these undesirable effects, and which provides improved performance.
This invention provides a flash memory cell having unique advantages over previous flash memory cells, together with a process for manufacturing such a cell and associated peripheral circuitry. The flash memory cell of this invention may be programmed and erased using substantially lower voltages than are employed in prior art flash memory cells. This provides advantages by enabling peripheral circuitry which supports the memory array and is on the same integrated circuit chip to be designed to handle lower voltages. This enables the use of smaller transistors, resulting in higher yields, greater reliability, and lower costs.
In a preferred embodiment, the flash memory cell structure of our invention includes a triple well integrated circuit structure. In particular, the memory cell includes a semiconductor substrate formed from first conductivity type material and having an upper surface. A first well region of second conductivity type extends into the substrate adjacent the surface, the second conductivity type being opposite to the first conductivity type. The first well includes within it a second well, also formed adjacent the surface of the substrate, and of first conductivity type material. A floating gate transistor is formed in the second well region, and includes a source region, a drain region, a floating gate disposed above the surface and electrically isolated from the substrate. The floating gate extends between the source and drain regions. A control gate is disposed above the floating gate. A first contact region is provided to the first well for controlling its potential, and a second contact region is provided to the second well for controlling its potential. As will be described, the use of multiple wells enables the memory cell to be programmed and erased with lower voltages than previously possible. It also minimizes the need for the peripheral circuitry to handle high potentials. The peripheral circuitry can be formed at any desired location depending on the properties desired, including in the first well, in the second well, or in the substrate outside both wells.
The invention also includes a process for fabricating an integrated circuit memory cell. In the preferred embodiment of the process, a semiconductor substrate of first conductivity type is employed. A first well region of second conductivity opposite to the conductivity of the first conductivity type is formed in the substrate and has a periphery. Within the periphery of the first well region, but also. adjacent the surface of the substrate, a second well region is formed. Preferably, the second well region is of first conductivity type. Also formed within the periphery of the first well region is a first contact region which is spaced apart from the second well region. The first contact region is of second conductivity type and is more conductive than the first well region. A first insulating layer is formed across the surface of the substrate, and a conductive layer is formed on the insulating layer to provide a floating gate which is disposed above the surface of the substrate and electrically isolated therefrom. On the surface of the first conductive layer, a second insulating layer is formed. Over the second insulating layer a second conductive layer is formed which provides a control gate. Using the control gate and the floating gate as a mask, dopants are introduced into the second well region to form a source region, and a drain region. During this process a contact region is also formed to contact the second well. The contact region is spaced apart from the source region and the drain region, and is more conductive than the second well.
The invention also includes a unique technique for programming memory cells. In a preferred embodiment, the memory cells are programmed by raising the control gate to a first potential no greater than 9.0 volts. The drain is raised to a potential no more than 5.0 volts. The source is coupled to ground potential, and the region of semiconductor material within which the source and drain are formed is placed at a potential below ground potential. In response to this condition, electrons are caused to move from the substrate channel through the insulating layer and onto the floating gate. Their presence (or absence) on the floating gate can be used to indicate the state of the memory cell.
The invention also includes a technique for erasing memory cells. Memory cells formed according to the invention may be erased by lowering the potential of the control gate to a potential no more negative than xe2x88x929.0 volts. The source and drain regions are disconnected from any potential source, and the semiconductor material within which the source and drain regions are formed is then placed at a potential no more positive than 8.0 volts. In response to this condition, any electrons trapped on the floating gate will be caused to tunnel through the intervening oxide over the channel and return to the substrate. As a result, the memory cell will be erased.
A particular advantage to the triple well flash memory of this invention is that a uniform erase may be performed instead of a nonuniform (source edge) erase. The uniform erase provides better endurance and data retention. The uniform erase is advantageous because the electrons tunnel through an insulating layer, eliminating the hot hole injection problems due to band-to-band tunneling and source edge erase which were problems of prior art devices. Hot hole degradation involves holes being trapped in the insulating oxide between the gate and source region. This results in leakage current and changes the erase characteristics.
An additional advantage of the triple well structure is that it allows independent control of the memory cell region substrate potential in contrast to the peripheral circuit substrate potential. In other words, the potential of the substrate in the region of the memory cells can be controlled independently of the potential of the substrate in the peripheral circuit regions. In contrast to prior art devices and processes, this enables the application of positive or negative voltage to the cell substrate, while simultaneously maintaining ground potential in the region of the peripheral devices. Such an approach allows for the uniform channel erase and the use of lower potentials.
In prior art flash memories, currents on the order of 20-30 milliamps were required to erase a block, and the use of channel erase was not feasible because the difference in potential between the substrate and the control gates could not be made large enough. Utilizing the techniques described here, erase currents for a block of cells can be reduced to on the order of 100 microamps. The low power and low current requirements of this invention make its applicability to battery-powered devices particularly advantageous.